Department of Mechatronics Engineering

EEE 420 | Course Introduction and Application Information

Course Name

FPGA (Field Programmable Gate Array) Design Using HDL (Hardware Description Language)

Code	Semester	Theory (hour/week)	Application/Lab (hour/week)	Local Credits	ECTS
EEE 420	FALL	2	2	3	6

Prerequisites	None
Course Language	English
Course Type	ELECTIVE_COURSE
Course Level	First Cycle
Mode of Delivery	Face to face
Teaching Methods and Techniques of the Course	Application: Experiment / Laboratory / Workshop
National Occupational Classification Code	-
Course Coordinator	Prof. Dr. Aydın Akan
Course Lecturer(s)	Prof. Dr. Aydın Akan
Assistant(s)	-

Course Objectives

This course covers the design of digital systems using VHDL and its implementation on FPGA. The unit will focus on design methodology, hardware modeling and high-level synthesis. A strong emphasis is placed on the design and implementation of working hardware implementations on FPGAs. Fundamentals of VHDL, digital design practices, and writing test benches for exercising the designs will be presented.

Learning Outcomes

The students who succeeded in this course;

Name	Description	PC Sub	* Contribution Level
Name	Description	PC Sub	1	2	3	4	5
LO1	Apply techniques and methods in digital systems design					X
LO2	Explain digital design flows in the system design			X
LO3	Describe HDL (Verilog or VHDL) language				X
LO4	Design digital circuits using FPGAs				X
LO5	Analyse complex digital circuits with HDL (Verilog or VHDL)				X

Course Description

Design Concepts, Introduction to Logic Circuits, Implementation Technology, An FPGA Primer, A VHDL Primer: The Essentials, Optimized Implementation of Logic Functions, Number Representation and Arithmetic Circuits, Combinational-Circuit Building Blocks, Design Automation and Testing for FPGAs.

Related Sustainable Development Goals

Course Category	Core Courses
	Major Area Courses	X
	Supportive Courses
	Media and Managment Skills Courses
	Transferable Skill Courses

WEEKLY SUBJECTS AND RELATED PREPARATION STUDIES

Week	Subjects	Required Materials	Learning Outcome
1	Design Concepts	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.1)	LO1
2	Introduction to Logic Circuits	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.2)	LO1
3	Implementation Technology	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.3)	LO1
4	An FPGA Primer	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 2)	LO2
5	A VHDL Primer: The Essentials	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 3)	LO3
6	A VHDL Primer: The Essentials	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 3)	LO3
7	A VHDL Primer: The Essentials	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 3)	LO3
8	Midterm	-	-
9	Optimized Implementation of Logic Functions	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.4)	LO4
10	Optimized Implementation of Logic Functions	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.4)	LO4
11	Number Representation and Arithmetic Circuits	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.5)	LO4
12	Combinational-Circuit Building Blocks	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.5)	LO5
13	Combinational-Circuit Building Blocks	Fundamentals of Digital Logic with VHDL Design Stephen Brown, Zvonko Vranesic (Chp.5)	LO5
14	Design Automation and Testing for FPGAs	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 4)	LO4
15	Design Automation and Testing for FPGAs	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson (Chp. 4)	LO4
16	Final	-	-

Course Notes/Textbooks	Fundamentals of Digital Logic with VHDL Design Stephen Brown Zvonko Vranesic
Suggested Readings/Materials	Design Recipes for FPGAs_ Using Verilog and VHDL-Peter Wilson

EVALUATION SYSTEM

Semester Activities	Number	Weighting	LO1	LO2	LO3	LO4	LO5
Midterm	1	20	X	X
Final Exam	1	40			X		X
Presentation / Jury	1	10				X
Quizzes / Studio Critiques	2	10	X	X
Laboratory / Application	1	20			X	X	X
Total	6	100

ECTS / WORKLOAD TABLE

Semester Activities	Number	Duration (Hours)	Workload
Participation	-	-	-
Theoretical Course Hours	16	2	32
Laboratory / Application Hours	16	2	32
Study Hours Out of Class	16	5	80
Field Work	-	-	-
Quizzes / Studio Critiques	2	2	4
Portfolio	-	-	-
Homework / Assignments	-	-	-
Presentation / Jury	1	10	10
Project	-	-	-
Seminar / Workshop	-	-	-
Oral Exams	-	-	-
Midterms	1	10	10
Final Exam	1	12	12
		Total	180